Digital data can be physically encoded as amplitude levels in an analog signal. For example, binary data consisting of logic highs and logic lows can be encoded as a waveform having voltage high and voltage low steps. The data-bearing analog signal can be communicated via an analog channel (e.g., between integrated circuits via a printed-circuit board) to a receiver, which must extract the digital data from the analog signal, e.g., by periodically sampling the analog signal.
“Sampling” refers to a process of determining an instantaneous parameter (e.g., voltage) value for an analog signal. For example, an instantaneous high voltage can indicate a logic high symbol, while an instantaneous low voltage can indicate a logic low symbol. Sampling results can vary according to the timing (phase) and reference levels applied. For example, invalid data (which may, nonetheless, be useful for some purposes) can result from sampling at the transitions between highs and lows or by using a reference level above or below the dynamic range of the analog signal. Valid data can be obtained by sampling between transitions and using a reference amplitude (e.g., voltage) near the center of the analog signal amplitude (e.g., voltage) range. Timing recovery circuits are available for extracting timing from the analog signal.
A “decision feedback equalizer” or “DFE” is a device that makes adjustments in a receiver based on previously determined (“decided”) symbol values. A DFE can be used to help set reference levels based on previously decided symbol values. The previously decided symbol values are multiplied by “tap coefficients” and the resulting products are summed to provide a reference level or a level from which a reference level can be derived. The tap coefficients can be set based on a calibration procedure using a training symbol sequence.